`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Yu Zihao
// 
// Create Date: 2021/08/06 17:24:04
// Design Name: 
// Module Name: cpu_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module cpu_tb();
reg clk, reset, s, load; 
reg [15:0] in;
wire [15:0] out;
wire N, V, Z, w;
cpu cpu_tb(.clk(clk),.reset(reset),.s(s),.load(load),.in(in),.out(out),.N(N),.V(V),.Z(Z),.w(w));

initial begin
    clk = 0;
    repeat(500) #5
    begin
        clk <= ~clk;
    end
end

initial begin
reset = 0;
#30;
reset = 1;
#20;
reset = 0;

//MOV R0,0x12
in=16'b11010_000_00010010;s=0;load=1;
#10;
s=1;load=0;
#10;
s=0;
#10
//MOV R1,0x32
in=16'b11010_001_00110010;s=0;load=1;
#10;
s=1;load=0;
#10;
s=0;
#10
//MOV R2,R0,sh_r2 ����һλ�ұ�����λ
in=16'b11000_000_010_11_000;s=0;load=1;
#10;
s=1;load=0;
#10;
s=0;
#30
//MOV R3,R2
in=16'b11000_000_011_00_010;s=0;load=1;
#10;
s=1;load=0;
#10;
s=0;
#30

$stop;
end

endmodule
